1. Field of the Invention
The present invention relates to a page buffer used in a NAND flash memory and the programming method thereof, and more particularly, to a page buffer used in a NAND flash memory and the programming method thereof providing cache function.
2. Description of the Related Art
Flash memory devices are generally classified into NOR flash memories and NAND flash memories. In NOR flash memories, the memory cells are connected in parallel to bit lines, resembling the parallel connection of transistors in CMOS NOR gates, and thus are known as NOR flash memory. The memory cells in NOR flash memories can be randomly accessed. Thus NOR flash memories are mainly used in BIOS of personal computers, or in firmware of ASIC. The memory cells in NAND flash memories, on the other hand, are connected in series resulting a smaller cell size than that of the NOR flash memories. Thus, NAND flash can provide a smaller die size and faster write and read time than NOR flash. However, the memory cells in NAND flash memories cannot be randomly accessed. Therefore, NAND flash memories are mainly used in storage devices, such as hard disks or memory cards.
Each memory cell in a NAND flash memory resembles a standard MOSFET, except that there is a floating gate below the control gate of each memory cell, wherein the floating gate is isolated by an oxide layer. Electrons placed on the floating gate will be trapped for years, modifying the threshold voltage of the cell. A traditional single layer cell (SLC) of a NAND flash memory may have a normal threshold voltage or a modified threshold voltage, and therefore provides two states, i.e., one bit, for the NAND flash memory. Recently, to increase the integration of memory cells of NAND flash memories, multi level cells (MLC), which provide more than one bit for the NAND flash memory, and therefore exhibit multiple threshold voltages, are widely utilized in NAND flash memories.
A conventional NAND flash memory comprises a memory cell array, a row decoder connected to the word lines of the memory cell array, and a page buffer connected to the bit lines of the memory cell array. FIG. 1 shows two string memory cells of a memory cell array of a conventional NAND flash memory. The memory cell array 20 comprises a plurality of memory cells 10 connected in series between a bit line (BL1 or BL2) and a ground select line GSL. A group of memory cells 10 connected in series to one bit line (BL1 or BL2) along with select transistors (a string select transistor SST and a ground select transistor GST) used to select the memory cells 10 is called a string. The string select transistor SST is selectively switched on to couple the associated string and the bit line together. The ground select transistor GST is selectively switched to control the connection between each string and a common source line CSL. Bit lines BL1 or BL2 are connected to a page buffer 30. Word lines WL1 to WL16, SSL and GSL are connected to a row decoder 40. The row decoder 40 determines which memory cells are programmed or read. The page buffer 30 performs the programming and reading operations of the selected memory cells.
U.S. Pat. No. 7,254,064 discloses a page buffer design comprising three latch circuits. Each memory cell comprises two bits: MSB and LSB. The programming operations include two MSB programming and one LSB programming. Two of the latch circuits are used in the MSB programming operation, and the remaining one is used for the cache function.
U.S. Pat. No. 7,009,878 discloses a page buffer design comprising two latch circuits. Each memory cell comprises two bits: MSB and LSB. The programming operations include two MSB programming and one LSB programming. The cache function is achievable in the LSB programming. The cache function is prohibited, however, in the MSB programming.
US patent 2008/0,008,008, herein incorporated by reference and hereinafter '008, discloses a page buffer design comprising two latch circuits. Each memory cell comprises two bits: MSB and LSB. The programming operations include one MSB programming and two LSB programming. The cache function is not implemented in this disclosure.
The cache function for the programming operation is not available in the aforesaid prior page buffer design utilizing two latch circuits, while the three latch circuit design requires too much die size. Therefore, there is a need to design a page buffer with cache function for the programming operation requiring only two latch circuits.